The present invention relates generally to bit or frame alignment techniques, and more specifically to a synchronizer for quickly reestablishing synchronization in digital transmission systems.
As shown in FIG. 1, a known frame synchronizer has a frame sync detector 103 which detects a particular bit pattern signifying the frame start timing of a data bit stream supplied through terminal 101 and supplies a logic-1 output to a coincidence gate 104 and a noncoincidence gate 105 upon detection of a frame bit pattern. Clock input pulses at terminal 102 are supplied through a control gate 108 to a frame counter 110 to generate a logic-1 output at frame intervals so that it coincides with the logic-1 output of frame sync detector 103 when data and clock inputs are in phase with each other at terminals 101 and 102.
When the data input is synchronized with the frame sync timing, a logic-1 output is supplied from coincidence gate 104 to sync guard counter 107 to reset it at frame intervals and a logic-0 output is applied to clock gate 108 to allow passage of input clock pulses to the counter 110, applying a logic-1 output to gates 104 and 105 at frame intervals therefrom. Under this condition, the frame synchronizer is a "forward guard mode". During this mode, possible bit errors in a frame pattern will cause a logic-1 output from noncoincidence gate 105 to be counted by sync guard counter 107 and a logic-1 output is not generated therefrom until the count of N is reached.
When the data input begins to lose frame synchronization, coincidence gate 104 produces a logic-0 output regardless of a logic-1 input from the sync pattern detector 103, while noncoincidence gate 105 produces a logic-1 output, which is counted by sync guard counter 107. At the count of N, a logic-1 output is applied to the clock gate 108 signifying that an outof-sync condition has continued for a period of N consecutive frames. Clock gate 108 is inhibited in response to this logic-1 output and the frame counter 110 enters a hunting mode, which continues until a frame sync pattern is detected the frame sync detector 103. In response to the detection of a frame sync pattern by detector 103, a logic-1 output is supplied to sync guard counter 107 from coincidence gate 104, resulting in the application of a logic-0 input to the clock gate 108 from sync guard counter 107. The frame synchronizer now enters a "backward guard mode" in which frame counter 110 resumes clock counting. During this mode, sync guard counter 107 responds to logic-1 inputs from the coincidence gate 104 by incrementing its count to M. On reaching the count M, the frame synchronizer recognizes that the data and clock inputs have been resynchronized for a period of M consecutive frames and it enters a "forward guard mode". Otherwise, the frame synchronizer recognizes that resynchronization has failed and the sync guard counter 107 produces a logic-1 output to cause the frame counter 110 to reenter the hunting mode. With this prior art frame synchronizer, however, hunting mode does not begin until the count of N is reached in the sync guard counter. Thus, in the worst case, the hunting would take as long as more than one frame interval. This is particularly disadvantageous for transmission systems in which loss of data occurs frequently due to high speed or lengthy frames. Thus, the resynchronization of the prior art synchronizer depends on the frame bit pattern (whether a long string of consecutive bits or bit interleaved with data) employed in a particular transmission system.
Bit synchronization between a data signal and a clock input is established prior to frame synchronization. In a known bit synchronizer shown in FIG. 2, a data signal is applied to a latch 201 and a clock input is applied to a tapped delay line formed by a series of gates 202 to generate plural clock pulses of successively shifted phases for application to a selector 204. A control signal is derived from a preamble contained in the data signal and applied to the selector 204 to selectively couple the clock pulses to the latch 201 to provide bit synchronization between the data signal and the clock signal. However, the use of analog circuit components for deriving different clock timing pulses requires precision and constant adjustment of the delays in accordance with the repetition frequency of the input data signal.